An experience report on implementing compile-time optimizations in galaxsim, documenting insights and practical understanding gained about both Verilog itself and the internal mechanisms of Verilog Compile Simulator.

Personal Learning Notes for the Course: Analysis and Design of System-on-Chip at BUPT.

A hands-on lab record detailing the use of open-source EDA tools: logic synthesis with Yosys, timing analysis via iSTA, and physical backend design using iEDA following its user_guide.

A concise guide to sliding window techniques — fixed and variable size windows, key patterns, and common tricks for solving array and substring problems in O(n).